`timescale 1ps/1ps
module SFI4_TEST_WRAP (
	CHNN0_DATA_TX_P,
	CHNN0_DATA_TX_N,
	CHNN0_CLOCK_TX_P,
	CHNN0_CLOCK_TX_N,
	CHNN0_INTERFACE_CLK_P,
	CHNN0_INTERFACE_CLK_N,
	
	CHNN0_DATA_RX_P,
	CHNN0_DATA_RX_N,
	CHNN0_CLOCK_RX_P,
	CHNN0_CLOCK_RX_N,

	OSC1_200M_P,
	OSC1_200M_N,

    RESET,
    RESET_DETECTOR,
    CAPTURE_FC,
	CAPTURE_TAP_COUNT,
	PAT_SEL,
	ERROR_INSERT,
	ERROR_COUNT_CHAN_SEL,
	TAP_COUNT_CHAN_SEL,
	MANUAL_DELAY_INC,
	MANUAL_DELAY_DEC,

    USER_LED
	);

input		RESET;			// ALL RESETS CASCADE FROM THIS RESET
input		RESET_DETECTOR;		// RESETS ONLY THE ERROR DETECTORS
input		CAPTURE_FC;		// STROBE TO CAPTURE FRAME_COUNT INTO SLOWER DOMAIN
input		CAPTURE_TAP_COUNT;	// STROBE TO CAPTURE TAP_COUNT INTO SLOWER DOMAIN		
input[3:0]	PAT_SEL;		// SELECTION OF TEST DATA PATTERN (e.g. PRBS23)
input 		ERROR_INSERT;           // FORCES ERRORS ACROSS 16 CHANNELS
input[3:0]	ERROR_COUNT_CHAN_SEL;	// SELECTS CHANNEL TO READ ERROR COUNT FROM
input[4:0]	TAP_COUNT_CHAN_SEL;	// SELECTS CHANNEL TO READ TAP COUNT FROM
input		MANUAL_DELAY_INC;	// MANUALLY INCREMENTS THE DATA DELAY
input		MANUAL_DELAY_DEC;       // MANUALLY DECREMENTS THE DATA DELAY  
output[6:1]     USER_LED; 
	
input[15:0]       CHNN0_DATA_RX_P;		// SOURCE SYNC DATA INPUT (P)
input[15:0]       CHNN0_DATA_RX_N;		// SOURCE SYNC DATA INPUT (N)
input             CHNN0_CLOCK_RX_P;		// SOURCE SYNC CLOCK INPUT (P)
input             CHNN0_CLOCK_RX_N;		// SOURCE SYNC CLOCK INPUT (N)

input             CHNN0_INTERFACE_CLK_P;	// TX CLOCK SOURCE FROM CLKMOD2 (P)
input             CHNN0_INTERFACE_CLK_N;	// TX CLOCK SOURCE FROM CLKMOD2 (N)
output[15:0]      CHNN0_DATA_TX_P;		// SOURCE SYNC DATA OUTPUT (P) 
output[15:0]      CHNN0_DATA_TX_N;              // SOURCE SYNC DATA OUTPUT (N) 
output            CHNN0_CLOCK_TX_P;             // SOURCE SYNC CLOCK OUTPUT (P)
output            CHNN0_CLOCK_TX_N;             // SOURCE SYNC CLOCK OUTPUT (N)

input           OSC1_200M_P;            // IDLYCTRL CLOCK
input           OSC1_200M_N;            // IDLYCTRL CLOCK


wire	[7:0]	TAP_COUNT;		// CURRENT IDELAY TAP SETTING (0-63)
wire		ARMED_FLAG;		// ERROR DETECTOR STATE: ARMED
wire		LOCKED_FLAG;            // ERROR DETECTOR STATE: LOCKED
wire		ABORT_FLAG;		// ERROR DETECTOR STATE: ABORT
wire		IDELAY_READY;		// IDELAYCTRL CIRCUIT IS LOCKED
wire    [31:0]  FRAME_COUNT;            // NUMBER OF FRAMES RECEIVED
wire	[31:0]	ERRORED_BITS;

wire    [35:0]  CONTROL0;               // ICON signal
wire    [35:0]  CONTROL1;               // ICON signal
wire    [95:0]  DEBUG_BUS;              // ILA signal
wire    [127:0] SYNC_IN;		// VIO signal
wire    [31:0]  SYNC_OUT;		// VIO signal
wire            ASYNC_OUT;		// VIO signal


SDR_4TO1_16CHAN_TOP TOP
	(
	.DATA_TX_P            (CHNN0_DATA_TX_P),
	.DATA_TX_N            (CHNN0_DATA_TX_N),
	.CLOCK_TX_P           (CHNN0_CLOCK_TX_P),
	.CLOCK_TX_N           (CHNN0_CLOCK_TX_N),
	
	.DATA_RX_P            (CHNN0_DATA_RX_P),
	.DATA_RX_N            (CHNN0_DATA_RX_N),
	.CLOCK_RX_P           (CHNN0_CLOCK_RX_P),
	.CLOCK_RX_N           (CHNN0_CLOCK_RX_N),
	
	.OSC1_200M_P          (OSC1_200M_P),
	.OSC1_200M_N          (OSC1_200M_N),
	.INTERFACE_CLK_P      (CHNN0_INTERFACE_CLK_P),
	.INTERFACE_CLK_N      (CHNN0_INTERFACE_CLK_N),
	
	.RESET                (RESET),
	.RESET_DETECTOR       (RESET_DETECTOR), 
	.USER_LED             ( USER_LED ),
	.ARMED_FLAG           (  ),
	.LOCKED_FLAG          (  ),
	.DISTRESS_FLAG        (  ),
	.ABORT_FLAG           (  ),
	.IDELAY_READY         (  ),
	.ERRORED_BITS         (  ),
	.FRAME_COUNT          (  ),
	.TAP_COUNT            (  ),
	.TRAINING_DONE        (  ),
	.LOCKED_DCM           (  ),
	
	.BERT_CAPTURE_FC      (CAPTURE_FC),
	.CAPTURE_TAP_COUNT    (CAPTURE_TAP_COUNT),
	.PAT_SEL              (PAT_SEL),   
	.ERROR_INSERT         (ERROR_INSERT),
	.ERROR_COUNT_CHAN_SEL (ERROR_COUNT_CHAN_SEL),
	.TAP_COUNT_CHAN_SEL   (TAP_COUNT_CHAN_SEL),

	.CLK200_O             (  ),
	.DEBUG_BUS            (  ),
	.MANUAL_DELAY_INC     (MANUAL_DELAY_INC),
	.MANUAL_DELAY_DEC     (MANUAL_DELAY_DEC)
	
	);


endmodule


